"With devices ranging from four to 20 high speed serial channels at speeds up to 3.125 Gbps and very low power consumption per channel, the Stratix GX family fits the bill in scaling up to a full, high-speed chassis or scaling down to the minimum requirement for a single line card," said Jeff Rhodes, business manager at Motorola Computer Group. "The flexibility of Altera's Mercury devices enabled us to implement our first generation Multi-Service Packet Transport Platform (MXP) in parallel with the emerging PICMG 2.20 switch fabric standard."

"The economics of 0.13-micron silicon are changing system architecture at a fundamental level, and the role of programmable technologies is becoming increasingly important as designers look for solutions that meet their requirements without painting them into a technological corner," said Jeremey Donovan, vice president and chief analyst with Gartner Dataquest's semiconductor group. "The melding of high-speed transceivers and programmable technology in particular is a logical outcome of the industry's new economic factors."

Low-Risk Path to Multi-Gigabit Design

Designed with up to 20 full-duplex transceiver channels, the Stratix GX family is well equipped to handle high throughput datapaths. This includes high-speed backplane and chip-to-chip communication technologies that are rapidly emerging in high-speed, data-intensive applications. Combining Stratix GX devices with the powerful Quartus® II design software and available IP cores optimized for transceiver applications gives system architects the power to get high-speed systems up and running in minimal time. More than just a robust transceiver on an FPGA, Stratix GX is a complete design platform that includes Gigabit Ethernet XAUI or SONET/SDH IP cores, models for system verification, and board layout guidelines. These are critical elements that designers need to create a working transceiver-based system for backplane or chip-to-chip applications.

Customer-Defined Features

As with the Stratix and Cyclone(TM) FPGA families, Altera once again brought customers from a wide array of markets into the product definition process. Faced with a common challenge-the need for reliable, high-speed data transfer across all design segments-Altera designed Stratix GX devices to include features specifically identified by customers as critical for successful design implementation.

     -- Tuned for backplane applications
          Stratix GX devices provide the rich features required for success in
          backplane applications.  Stratix GX devices provide both 40-inch FR4
          drive capability and receiver equalization.  Devices also include
          hot-socketing capability.
     -- Low transceiver power consumption
          At 75mW per channel and only 450mW per gigabit transceiver block,
          Stratix GX transceivers consume less than half the power of
          competing FPGA solutions.  In addition, Stratix GX devices support
          independent power down of either the transmit or receive channels.
          Low power consumption increases reliability and reduces cost.
     -- Support for a high-speed protocols such as XAUI and SONET/SDH
          The Stratix GX architecture is the only FPGA and multi-gigabit
          solution in the industry that includes dedicated circuitry for
          backplane applications in both XAUI and SONET/SDH systems.  XAUI-
          specific features include dedicated rate-matching, word-aligning,
          and clock-management circuitry.  Devices include dedicated silicon
          to perform SONET/SDH pattern detection and SONET/SDH pattern
          transmission, and to support both an 8- and 16-bit wide data bus
          without the 8B/10B encoder/decoder.  The dedicated circuitry
          increases reliability and provides time-to-market and cost
          advantages.
     -- Hard DPA for source synchronous I/O pins
          The industry's only embedded silicon implementation of dynamic phase
          alignment (DPA) circuitry provides a high-speed complement to the
          transceiver bandwidth.  DPA simplifies high-speed board design and
          layout through the automatic elimination of skew introduced by
          unmatched trace lengths, jitter, and other skew-inducing effects.
          Hard DPA (vs. soft DPA) specifically provides better immunity to
          temperature or voltage variation and much lower power consumption.
     -- The right logic densities for the transceiver channel count
          For high transceiver channel count applications, the Stratix GX
          architecture provides a more optimized channel-to-logic ratio than
          alternative solutions.  Stratix GX devices provide reduced logic
          options due to the significant use of dedicated silicon to address
          both transceiver and source-synchronous applications.

"As the only second-generation product in the market, we're well ahead of our competitors. Stratix GX FPGAs have the advantage of including Altera's experience of having worked with customers implementing multi-gigabit transceivers into their designs," said Tim Colleran, vice president of product marketing at Altera. "Our intention is to pass on this experience as a competitive advantage to our customers building high-speed applications, allowing them to get their products to market faster and with less risk."

Software Support

A beta version of Quartus II version 2.1 with support for Stratix GX has been shipping to customers since June of this year. A design kit specifically targeted for Stratix GX is now available through local Altera representatives as a complement to the Quartus II version 2.1 software. Quartus II version 2.1 provides support for system-level design with advanced features and tools such as LogicLock(TM), SOPC Builder, DSP Builder, board-level timing analysis tools, and signal integrity analysis tools. Quartus II provides the ideal development tool for meeting the design challenges of multi-million gate designs. It supports major operating systems such as Windows XP, Windows NT, Windows 98, Windows 2000, Sun Solaris, HP-UX, and Linux operating system.

Packaging, Pricing, and Availability

Stratix GX devices will be available in the 672-pin and 1,020-pin FineLine BGA® packages. The first device, the EP1SGX25D in the 1,020-pin FineLine BGA package will begin shipping in Q1 2003. Devices in the family will be as low as $99 in 50,000 unit volumes by mid-2004.

About Stratix GX FPGAs

The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-micron process technology with 1.5-V core voltage. Stratix GX devices have up to 20 embedded 3.125-Gbps transceivers and up to 45 differential I/O pins with dedicated dynamic phase alignment capability supporting up to 1-Gbps source-synchronous data transfers. Stratix GX devices also offer up to 41,250 logic elements (LEs), 3.27 Mbits of TriMatrix(TM) memory, 14 DSP blocks, eight phase locked loops (PLLs), Terminator(TM) technology for impedance matching, and signal integrity and advanced I/O buffers capable of interfacing with high-speed memory devices such as DDR SDRAM, QDR SRAM, QDR II SRAM, ZBT SRAM, DDR FCRAM and SDR SRAM devices. More technical information about the Stratix GX device family is available at www.altera.com/stratixgx.

About Altera

Altera Corporation is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.

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    Editor Contact:
     Anna Del Rosario
     Altera Corporation
     408-544-6397
     newsroom@altera.com